FAIRCHILD SEMICONDUCTOR

Fairchild TTL Family

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Table of Contents

Introduction ................. 3

Numerical Index of Devices .... 4

54/74 Index ............... .. 6 Specifications DON fa buatas Soe eGad eee see 7 MSl eesennw eet teehee tes 11 Memory ................-.. 63 Interface ................. 73 Package Drawings ............ 80 Loading Chart ............... 81 Pin: Diagrams: x26 s4-36443Ge43oe 88 Ordering Information .......... 108

INTRODUCTION

Fairchild’s TTL Family is the most complete line of TTL products available today. There are over 150 circuit functions with more than 75 MSI devices from which to choose. The family consists of logic, memory and interface functions, and is a unique blend of Fairchild proprietary circuits and a large number of second source devices which have achieved wide market acceptance.

Fairchild’s family of functions has been designed to provide the system designer with a complete line of standard, off-the-shelf functional building blocks that can be interfaced directly with each other in the same system to provide almost any Speed/ Power combination.

The typical characteristics of the Fairchild TTL Family are as follows. Full loading information is given on pages 81 to107.

Supply Voltage 5.0 V Logic ‘0’ Output Voltage 0.2 V Logic ‘1’? Output Voltage 3.0 V Noise Immunity 1.0 V Temperature Ranges 0°C to +70°C

—55°C to +125°C Packages 14, 16 and 24 Lead Dip and Flat Pack

NUMERICAL INDEX OF DEVICES

4100 (See 93400) 4101 (See 93401) 4102 (See 93402) 4103 (See 93403) 4106 (See 93406) 4108 (See 93408) 4110 (See 93410)

5400 (QNO0) 5401 (9NO1) 5402 (QNO2) 5403 (9NO3) 5404 (9NO4)

5405 (9NO5) 5408 (QNO8) 5410 (9N10) 5411 (9N11) 5420 (9N20)

5446 (9357A) 5447 (9357B) 5448 (9358) 5449 (9359) 5450 (9N50)

5451 (9N51) 5453 (9N53) 5454 (9N54) 5460 (QN60) 5470 (9N70)

5472 (9N72) 5473 (9N73) 5474 (9N74) 5475 (9375) 5476 (9N76)

DEVICE

5477 (9377) 5480 (9380) 5482 (9382) 5483 (9383) 5486 (QN86)

5490 (9390) 5491 (9391) 5492 (9392) 5493 (9393) 5494 (9394)

5495 (9395)

' 5496 (9396)

54104 (9N104) 54105 (9N105) 54107 (9N107)

54141 (9325) 54181 (9341)

54182 (9342) 54192 (9360) 54193 (9366)

54H00 (9H00) 54HO1 (9HO1) 54HO04 (9H04) 54HO5 (9H05) 54H10 (9H10)

54H20 (9H20) 54H22 (9H22) 54H30 (9H30) 54H40 (9H40)

54H73 (9H73) 54H76 (9H76) 54H78 (9H78)

DEVICE

7400 (QNO0) 7401 (9NO1) 7402 (9N02) 7403 (QNO3) 7404 (QN04)

7405 (QNO5) 7408 (QNO8) 7410 (9N10) 7411 (9N11) 7420 (9N20)

7430 (9N30) 7440 (9N40) 7441 (9315) 7442 (9352) 7443 (9353)

7444 (9354) 7446 (9357A) 7447 (9357B) 7448 (9358) 7449 (9359)

7450 (9N50 7451 (QN51 7453 (9N53 7454 (9N54 7460 (QN60)

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7470 (9N70) 7472 (9N72) 7473 (9N73) 7474 (9N74) 7475 (9375)

7476 (9N76) 7477 (9377) 7480 (9380) 7482 (9382) 7483 (9383)

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DEVICE

7486 (QN86) 7490 (9390) 7491 (9391) 7492 (9392) 7493 (9393)

7494 (9394) 7495 (9395) 7496 (9396)

74104 (9N104) 74105 (9N105) 74107 (9N107)

74141 (9325) 74181 (9341)

74182 (9342) 74192 (9360) 74193 (9366)

74196 (93H70) 74197 (93H76)

74H00 (9HO0) 74HO1 (9HO1)

74H05 (9HO5)

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( 74H04 (9H04) ( 74H10 (9H10)

74H20-(9H20) 74H22 (9H22) 74H30 (9H30) 74H40 (9H40)

74H73 (9H73) 74H76 (9H76) 74H78 (9H78)

7524 (9664) 7525 (9665)

NUMERICAL INDEX OF DEVICES

DEVICE

9000 9001 9002 9003 9004

9005 9006 9007 9008 9009

9012 9014 9015 9016 9017

9020 9022 9024 9033 (See 93433) 9034 (See 93434) 9035 (See 93435)

9N00/5400, 7400 9N01/5401, 7401 9N02/5402, 7402 9N03/5403, 7403 9N04/5404, 7404

9N05/5405, 7405 9N08/5408, 7408 9N10/5410, 7410 9N11/5411, 7411 9N20/5420, 7420

9N30/5430, 7430 9N40/5440, 7440 9N50/5450, 7450 9N51/5451, 7451 9N53/5453, 7453

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DEVICE

9N54/5454, 7454 9N60/5460, 7460 9N70/5470, 7470 9N72/5472, 7472 9N73/5473, 7473

9N74/5474, 7474 9N76/5476, 7476 9N86/5486, 7486

9N104/54104, 74104 9N105/54105, 74105 9N107/54107, 74107

9L00 9L04 9L24 9L54

9HO00/54HO00, 74HOO 9HO1/54H01, 74H01 9H04/54H04, 74H04 9HO5/54H05, 74H05 9H10/54H10, 74H10

9H20/54H20, 74H20 9H22/54H22, 74H22 9H30/54H30, 74H30 9H40/54H40, 74H40

9H73/54H73, 74H73 9H76/54H76, 74H76 9H78/54H78, 74H78

9300 9301 9304 9305 9306

9307 9308 9309 9310 9311

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DEVICE

9312 9314 9315/7441 9316 9317

9318 9321 9322 9324 9325/54141, 74141

9327 9328

9334

9337

9338

9340

9341/54181, 74181 9342/54182, 74182 9348

9350

9352/5442, 7442 9353/5443, 7443 9354/5444, 7444 9356

9357A/5446, 7446 9357B/5447, 7447 9358/5448, 7448 9359/5449, 7449 9360/54192, 74192 9366/54193, 74193 9375/5475, 7475 9377/5477, 7477 9380/5480, 7480 9382/5482, 7482 9383/5483, 7483 9390/5490, 7490 9391/5491, 7491 9392/5492, 7492 9393/5493, 7493 9394/5494, 7494 9395/5495, 7495 9396/5496, 7496 93L.00

93L01

DEVICE

93L08 93L09

93L10

93L11

93L12

93L14

93L16

93L18

93L21

93L22

93L24

93L28

93L40 93HO00 93H70/74196 93H72 93H76/74197 93400/B 93401

93402

93403

93406

93407

93410 93412 93415 93433 93434 93435 9600 9601 9602 9614 9615 9616 9617 9620 9621 9622 9624 9625 9644 9664/7524 9665/7525

54/74 SERIES INDEX

The following is a quick-look index to Fairchild second-sourced devices in the popular 5400/7400 series.

SERIES 54 (Standard) SERIES 54H (HighSpeed) SERIES 74 (Standard) SERIES 74H (High Speed)

DEVICE

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SERIES 74S (Super High Speed)

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DEVICE

74S00 74S01 74804 74805 74820 74822 74840 748112 748113 748114

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= TTL/SSI

INTRODUCTION The Fairchild TTL/SSI line offers the designer a broad selection of gates and flip flops for use with Fairchild MSI, Interface and Memory products in implementing TTL system designs. A total of 56 TTL/SSI functions are available for use in military and industrial temperature range applications. These products are available in the popular Dual In-Line package as well as Flat packages. All Fairchild TTL products are logic and supply voltage compatible so that circuit families may be mixed within a system for optimum

speed, power and economy.

9N/54, 74 SERIES TTL/SSI FEATURES

10 ns Typical Gate Delay 10 mW Typical Gate Power Dissipation Input Clamp Diodes Minimize Termination Effects Military and Industrial Temperature Range Available in DIP and Flat Packages 26 Functions Available

9000 SERIES TTL/SSI -FEATURES . 8 ns Typical Gate Delay 10 mW Typical Gate Power Dissipation ‘Input Clamp Diodes Reduce Termination Effects Darlington Output Stage Increases Circuit Speed Military and Industrial Temperature Range Available in DIP and Flat Packages 18 Functions Available

9L SERIES LPTTL/SSI FEATURES

20 ns Typical Gate Delay 2 mW Typical Gate Power Dissipation Input Clamp Diodes Minimize Termination Effects Darlington Output Stage Increases Circuit Speed Military and Industrial Temperature Range Available in DIP and Flat Packages.

9H/54H, 74H SERIES HSTTL/SSI FEATURES e 6ns Typical Gate Delay '22mW Typical Gate Power Dissipation Input Clamp Diodes to Minimize Termination Effects Darlington Output Stage to Increase Circuit Speed Military and Industrial Temperature Range e Available in DIP and Flat Packages _11 Functions Available

DESCRIPTION

The 9N/54, 74 Series is a broad family of SSL devices which are pin and function iden- tical with the popular 7400 series. These gates and binaries are available in industrial and military temperature ranges in both DIP and Flat packages. The line includes NAND gates, NOR gates, Exclusive-OR gates, AND gates, open collector gates as well as single and dual flip flops.

DESCRIPTION

The 9000 Series of gates and flip flops offers a family of high speed functions with speed and power specifications in between the 9N/ 54, 74 Series and the 9H/54H, 74H Series. The Darlington output stage provides faster switching times and increased capacitive drive capability over the 9N/54, 74 Series.

DESCRIPTION

The 9L Series of low power TTL gates and flip flops offers a speed/power trade-off well suited to both industrial and military applica- tions. The power is one fourth that of a stand- ard TTL gate and typical system speeds of up to 10 MHz are possible. The 9L Series TTL/ SSI functions are used with the 93L low power TTL/MSI devices to implement low power, moderate speed systems.

DESCRIPTION

The 9H/54H, 74H Series is a line of high speed gates and flip flops which are pin and function identical with the popular 74H00 Series.

These devices are used with the 9300 and 93H Series of TTL/MSI devices to implement high speed logic functions in digital systems.

TTL/SSI e GATES e FLIP-FLOPS

STANDARD

tog = 10 ns P, = 10 mW per Gate

NAND GATES to +70°C —55° to +125°C

Quad 2-Input Positive NAND Gate 9N01/7401

Dual 4-Input Positive NAND Gate 9N20/7420 9N20/5420 | 8-Input Positive NAND Gate 9N30/7430 9N30/5430

NOR GATES

Quad 2-Input Positive NOR Gate 9N02/7402 Quad 2-2-2-4-Input Positive NOR Gate

AND GATES

Quad 2-Input Positive AND Gate 9N08/ 7408

Quad 2-Input Positive AND Gate (Open Collector) 9NO09/ 7409 Triple 3-Input Positive AND Gate 9N11/7411

EXCLUSIVE-OR GATES

Quad Exclusive-OR Gate 9N86/ 7486

Quad Exclusive-OR Gate with Inverted Outputs

9N00/5400 9NO01/5401 9N03/5403

9N02/5402

9N08/5408 9N09/5409

9N11/5411

9N86/5486

AND-OR-INVERT GATES AND EXPANDERS

INVERTERS AND BUFFERS

Hex Inverter with Open-Collector Output 9N05/ 7405 Dual 4-Input Positive NAND Buffer 9N40/7440

FLIP-FLOPS J-K Flip-Flop 9N70/7470 J-K Master Slave Flip-Flop 9N72/7472

Dual J-K Flip-Flop

9N51/5451 9N50/5450 9N54/5454 9N53/5453

9N60/5460

9N04/5404 9N05/5405 , 9N40/5440

9N70/5470 9N105/54105

9N72/5472 9N104/54104

Dual J-K Master Slave Flip-Flop

9N73/7473 9N107/74107

9N73/5473 9N107/54107

Dual J-K Master Slave Flip-Flop with Separate Preset and Clear 9N76/ 7476 9N76/5476 Dual D-Type Edge-Triggered Flip-Flop 9N74/7474 9N74/5474

TTL/SSI ¢ GATES ¢ FLIP-FLOPS

LOW POWER HIGH SPEED

t.g = 8ns t.g = 20 ns tog = 6ns P, = 10 mW per Gate P, = 2 mW per Gate P, = 22 mW per Gate

sat eee yer errs —55° to +125°C to +70°C Pozar | 9HOT/54H01 a ee ee eee

SUPER HIGH SPEED

P; = 19 mW per Gate

9H08/74H08 9H08/54H08

9H11/74H11 9H11/54H11

9H51/54H51 9H50/54H50 9H54/54H54 9H53/54H53

9H50/74H50 9H54/74H54

9H60/54H60*

=e 9S04/74S04 9S05/74S05 9S40/74S40

9H04/74H04 9H04/54H04 9H05/74H05 9HO05/54H05 9H40/74H40 9H40/54H40

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9H72/54H72

9H73/54H73 9S113/74S113 9H78/54H78 9S114/748114 9H76/54H76 9$8112/74S8112

* TO BE ANNOUNCED

Photomicrograph of the TTL/MSI 9340 Arithmetic Logic Unit Showing Dual Layer Metal Technology

10

TTL/MSI

INTRODUCTION The Fairchild TTL/MSI product line includes 75 complex digital logic functions, including standard, high speed, and low power circuits. The use of complex TTL functions in the design of new digital systems can significantly reduce package count and systems cost while providing smaller size, increased reliability, and greater overall system speed. The Fairchild TTL/MSI product line is divided into 7 functional categories and contains standard, high speed and low power complex circuits.

The table below summarizes the Fairchild TTL/MSI product line.

SUPER STANDARD LOW POWER HIGH SPEED HIGH SPEED REGISTERS TTL TTL TTL TTL

4-Bit Shift Register ee, a5io0 nenee

4-Bit Shift Register With Clock Enable Beers: fee ee: 4-Bit Right/Left Shift Register 9395/7495 | | 9396/7406 |

5-Bit Shift Register

8-Bit Shift Register 9391/7491 Dual 8-Bit Shift Register 9328 8-Bit Multiple Port Register 9338

ENCODERS

OPERATORS

| DualFull Adder 8804 9380/7480 | | 2BitFullAdder 9882/7482 | | 4BitFullAdder 9888/7483 |

aa Craene ee 9340 4-Bit Arithmetic Logic Units 9341/74181 - 93L40

Carry Lookahead 9342/74182 | si 12-Input Parity Checker/Generator 9348 teat Seats Seer ead

DECODERS /DEMULTIPLEXERS | BCD To Decimal Decoder Cd 9952/7442 |

Excess - 3 To Decimal Decoder 9353/7448 | | Excess - 3 Gray To Decimal Decoder 9354/7444, | eT One of Sixteen Decoder 9311 93L11 ae eee

931.21

9317 Seven Segment Decoder/ Driver 9327 9337

' 9357A/7446 BCD To Seven Segment Decoder/Driver 9357B/7447 aaa 9358/7448 BCD To Seven Segment Decoder 9359/7449

* TO BE ANNOUNCED

11

TTL/MSI ¢ MULTIPLEXERS ¢ LATCHES e COUNTERS

_ ; SUPER STANDARD LOW POWER HIGH SPEED HIGH SPEED MULTIPLEXERS TTL TTL TTL TTL [Quad Two Input Multiplexer —“‘;SSOCNOOt(OBOR:”OTCOBLOQQ—s—CiadT aes‘ (TU | Dual Four Input Multiplexer —“‘C;SCC(#*”YSOO#O#(#BOOSCO#OC*C;=SCi‘éOLDS:C—C ‘<TC | Eight Input Multiplexer —“‘“C™NCO!O!O!OC*L!OO#C(+éZV2:”S~SCOT SC siCe2—“ (eT CT LATCHES Four Bit Latch 9375/7475 9377/5477 9308 COUNTERS

9350 Decade Counter 9390/7490

Decade Counter 9310 Up/Down Decade Counter (Dual Clock) 9360/ 74192 Up/Down BCD Counter 9306

Binary Counter anon Tb4 4-Bit Binary Counter 9316

Up/Down Binary Counter (Dual Clock) 9366/ 74193 Divide By Twelve Counter 9392/7492

Variable Modulo Counter * TO BE ANNOUNCED

12

STANDARD TTL/MSI ¢ REGISTERS

9300

4-BIT UNIVERSAL SHIFT REGISTER

DESCRIPTION The 9300 is a synchronous 4-bit shift register de- signed to perform functions such as storage, shifting, counting and serial code conversion. It has assertion outputs on each stage and a negation output on the last stage, an overriding asynchronous master reset, JK input configuration, and a syn- chronous parallel load facility.

Data entry is synchronous with the registers changing state after each low to high transition of the clock. With the parallel enable low the parallel inputs determine the next condition of the shift register. When the parallel enable input is high the shift register performs a one bit shift to the right, with data entering the first stage flip-flop through JK inputs. By tying the two inputs together D type entry is obtained.

The asynchronous active low master reset when activated over- rides all other input conditions and clears the register.

TRUTH TABLE FOR SERIAL ENTRY

Q, at t, (no change) Q, at t, (toggles) , :

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= HIGH, MR = HIGH, (n + 1) indicates state after next clock

PE

PE PoP; Po P3 9300 SHIFT RESIS RG MR Q0Q1 0293 “3

PIN NAMES LOADING PE Parallel Enable (Active Low) Input 2.3 UL Po, Pi, Pz, P3 Parallel Inputs 1 UL J First Stage J (Active High) Input 1 UL K First Stage K (Active Low) Input 1 UL CP Clock(Active High Going Edge)Input 2 UL MR Master Reset (Active Low) Input 1 UL Qo, Qi, Q2, Q3 Parallel Outputs 6 UL Q@ Complementary Last Stage Output 6 UL CHARACTERISTICS

TYPICAL SPEED TYPICAL DELAY

25 MHz Shifting Frequency CPtoQ 23ns

PACKAGE 16 Pin Dip (7B) or Flat Pack (4L) TYPICAL POWER é DISSIPATION 300 mW

13

STANDARD TTL/MSI ¢ REGISTERS

9328 DUAL 8-BIT SHIFT REGISTER

DESCRIPTION The 9328 is a Dual 8-bit synchronous shift regis- ter which can be used in high speed serial storage applications. Each register has a true and complemented output from the last stage, 2-input multiplexer with data select control at the input, and a two input clock OR gate input. A common clock, obtained by internally tying one input of each clock OR gate together, and overriding asynchronous master reset are common to both reg- isters.

Data entry is synchronous with the registers changing state after each low to high transition of the clock. Serial data enters through Do when the data select line is low and through Di, when the data select line is high. The clocking scheme employed allows the three clock inputs to be used in the following ways: one clock common with two separate clocks; one clock common with a separate active low clock enable input for each 8 bit shift register, and two separate clocks and one common active low clock enable input.

The asynchronous active low master reset when activated over- rides all other input conditions and clears the register.

LOGIC EQUATION FOR DATA ENTRY Sp Ds+ Do + Ds: Di

no s Qo s Q, ) > i cp . R Cp Qofo R Cp Qf Rc ea yl

cp

Po ; s Qo zi s Q} Hi Q@2 ) > cp cP cp R Cd Q@oP R Cp Q4p R Cp Q@2P )

14

Ds

Do Dy 9328 (7 8 BIT SHIFT

PIN NAMES LOADING Ds Data Select Input 2 UL Do, D1 Data Inputs 1 UL CP OR Clock Active High Going Edge Inputs Common 3.0 UL. ae Separate 1.5 UL MR Master Reset (Active Low) Input 1 UL Qr Last Stage Output 6 UL. Q7 Complementary Output 6 UL CHARACTERISTICS TYPICAL DELAY CP to.Q 17ns TYPICAL SPEED 30MHz_ Shifting Frequency

PACKAGE 16 Pin Dip (7B) or Flat Pack (4L) TYPICAL POWER DISSIPATION 300 mW

Ss Q4 cP R Cp Q4fO0

9338

8-BIT MULTIPLE PORT REGISTER

DESCRIPTION The 9338 is a multiple port register designed for high speed random access memory applications where the ability to simultaneously read and write is desirable. Acommon use would be as a register bank in a three address computer. Data can be written into any one of 8 bits, and read from any two of the 8 bits simultaneously.

It is organized as a master slave register that has eight masters and two slaves. Data on the Dainput is stored in the master selected by the write address inputs synchronously with the clock pulse (CP). Data from the eight masters is selected by the two independent read address fields and applied to the two slave flip flops. The slaves are controlled by the slave enable input, such that when the slave enable is held high, the masters store on the rising clock and the slaves store on a falling clock thus produc- ing normal master slave operation. If the slave enable is held low the slave flip flops are continuously enabled allowing immediate transfer of information from the master flip flops to the output.

CHARACTERISTICS TYPICAL DELAY CPtoZ 35ns

PACKAGE 16 Pin Dip (7B) or Flat Pack (4L) TYPICAL POWER DISSIPATION 265 mW Da \/ Ay > A, >> Ap >> 0

VV VV VV VY

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STANDARD TTL/MSI e REGISTERS

9338 Bo 8 BIT B, MULTIPLE PORT REGISTER

Ze 2c

PIN NAMES LOADING Ao, Al, Az Write Address Inputs 2/3 UL Da Data Input 2/3 UL Bo, Bi, Bz B Read Address Inputs 2/3 UL ZB B Output 10 UL Co, Ci, C2 C Read Address Inputs 2/3 UL Zc C Output 10 UL CP Clock Active High

Going Edge Input 2/3 UL SLE Slave Enable (Active Low) Input 2/3 UL

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STANDARD TTL/MSI REGISTERS

9391/5491,7491 8-BIT SHIFT REGISTER

DESCRIPTION The 9391/5491, 7491 is a serial-in, serial-out, 8-bit shift register utilizing transistor-transistor logic (TTL) cir- cuits, and is composed of eight R-S master-slave flip-flops, input gating, and a clock driver. The register is capable of storing and transferring data at clock rates up to 18 MHz while maintaining a typical noise-immunity level of 1 volt. Power dissipation is typically 175 milliwatts, and a full fan-out of 10 is available from the outputs.

Single-rail data and input control are gated through inputs A and B and an internal inverter to form the complementary inputs to the first bit of the shift register. Drive for the internal common clock line is provided by an inverting clock driver. Each of the inputs (A, B, and CP) appear as only one TTL input load.

The clock pulse inverter/driver causes these circuits to shift information to the output on the positive edge of an input clock pulse, thus enabling the shift-register to be fully compatible with other edge-triggered synchronous functions.

PIN NAMES LOADING A,B Data Inputs TUL Cp Clock Input 1 UL Q Complementary Data Output 10 UL Q Data Output 10 UL

CHARACTERISTICS

SHIFT FREQUENCY 18 MHz POWER DISSIPATION 175 mW PACKAGE 14 Pin DIP (6A) and Flat Pack (31)

A INPUT B

cp

A B

CP 9391/7491 Q Q

TRUTH TABLE

NOTES: 1. tn = bit time before clock.

2. tn +8 = bit time after 8 clock pulses

OUTPUT

16

STANDARD TTL/MSI © REGISTERS

9394/5494,7494 4-BIT SHIFT REGISTER

DESCRIPTION The 9394/5494, 7494 shift register is composed of four R-S master-slave flip-flops, four AND-OR-INVERT gates, and four inverter-drivers. Internal interconnections of these func- tions provide a versatile register which performs right-shift oper- ations as a serial-in, serial-out register or as a dual-source, parallel-to-serial converter. A number of these registers may be PE, Pin Pon Pip Pop Pic Poc Pip Pap connected in series to form an n-bit register.

9394/7494

CP C.

All flip-flops are simultaneously set to the logical 0 state by applying a logical 1 voltage to the clear input. This condition may be applied independent of the state of the clock input, but not independent of state of the preset input. Preset input is inde- pendent of the clock and clear states.

The flip-flops are simultaneously set to the logical’ 1 state from

t AD either of two preset input sources. Preset inputs Pj, through Pyp noes ROR are activated during the time that a positive pulse is applied to Pi, - Pop Preset Inputs 1 UL preset 1 if preset 2 is at a logical 0 level. When the logic levels PE, Preset 1 Input AUL at preset 1 and preset 2 are reversed, preset inputs Poathrough PE, Preset 2 Input 4UL Pap are active. D, Serial Data Inputs 1 UL

CP Clock Input 1 UL Cc, Clear Input 1 UL Transfer of information to the outputs occurs when the clock Qo Serial Data Output 10 UL input goes from a logical 0 to a logical 1. Since the flip-flops are R-S master-slave circuits, the proper information must ap- pear at the R-S inputs of each flip-flop prior to the rising edge CHARACTERISTICS of the clock input waveform. The serial input provides this in- formation for the first flip-flop. The outputs of the subsequent CLOCK FREQUENCY 15 MHz flip-flops provide information for the remaining R-S inputs. The PROPAGATION DELAY (CP toQ,) 25ns clear input and either preset 1 or preset 2 must be at a logical 0 POWER DISSIPATION 175 mW when clocking occurs. PACKAGE 16 Pin DIP (6B) PRESETS r ae | PE (PRESET 2)

PE; >

(PRESET 1)

Qp (OUTPUT) Ds (SERIAL INPUT) CP (CLOCK) C. (CLEAR)

17

Fe eee es STANDARD TTL/MSI ¢ REGISTERS \9395/5495,7495 4-BIT(RIGHT/LEFT)SHIFT REGISTER

DESCRIPTION This monolithic shift register is composed of four R-S master-slave flip-flops. Internal interconnections of these functions provide a versatile register which will perform right- shift or left-shift operations dependent upon the logical input level to the mode control. A number of these registers may be connected in series to form an n-bit right-shift or left-shift regis- o}CP)M Pa PR Pc Pp ter. This register can also be used as a parallel-in, parallel-out oO CPo 9395/7495

storage register with gate (mode) control. Dg A O& Q

When a logical 0 level is applied to the mode control input, the number-1 AND gates are enabled and the number-2 AND gates are inhibited. In this mode the output of each flip-flop is coupled to the R-S inputs of the succeeding flip-flop and right-shift oper- ation is performed by clocking at the clock 1 input. In this mode, serial data is entered at the serial input. Clock 2 and parallel inputs P, through P, are inhibited by the number-2 AND gates.

When a logical 1 level is applied to the mode control input, the PIN NAMES LOADING number-1 AND gates are inhibited (decoupling the outputs from the succeeding R-S inputs to prevent right-shift) and the num-

ber-2 AND gates are enabled to allow entry of data through CP, Clock 1 Input 1 UL parallel inputs P, through Pp, and clock 2. This mode permits CP, Clock 2 Input 1UL parallel loading of the register, or with external interconnection, M Mode Control Input 2 UL shift-left operation. In this mode, shift-left can be accomplished PasPas Pos Pp Parallel Data Inputs 1 UL by connecting the output of each flip-flop to the parallel input of Qs Qa, Qe, Qp Parallel Data Outputs 10 UL the previous flip-flop (Q, to input P.and etc.), and serial data Ds Serial Data Input 1 UL

is entered at input P,

Clocking for the shift register is accomplished through the AND-

OR gate E which permits separate clock sources to be used for

the shift-right and shift-left modes. If both modes can be clocked SHAnACTENIS uC?

from the same source, the clock input may be applied commonly ; to clock 1 and clock 2. Information must be present at the R-S CLOCK FREQUENCY 31 MHz

inputs of the master-slave flip-flops prior to clocking. Transfer PROPAGATION DELAY (CP toQ) 25ns of information to the output pins occurs when the clock input POWER DISSIPATION 250 mW goes from a logical 1 to a logical 0. PACKAGE 14 Pin DIP (6A)

OUTPUTS

(CLOCK 1) CP. (CLOCK 2)

laa OF CLOCK

p. (SERIAL S INPUT)

(MODE CONTROL )

INPUTS

18

STANDARD TTL/MSI ¢ REGISTERS

9396/5496,7496 5-BIT SHIFT REGISTER

DESCRIPTION The 9396/5496, 7496 consists of five R-S master- slave flip-flops connected to perform parallel-to-serial or serial- to-parallel conversion of binary data. Since both inputs and out- puts to all flip-flops are accessible, parallel-in/parallel-out or serial-in/serial-out operation may be performed.

All flip-flops are simultaneously set to the logical 0 state by ap- plying a logical 0 voltage to the clear input. This condition may be applied independent of the state of the clock input.

The flip-flops may be independently set to the logical 1 state by applying a logical 1 to both the preset input of the specific flip-flop and the common parallel load input. The common par- allel load input is provided to allow flexibility of either setting each flip-flop independently or setting two or more flip-flops simultaneously. Parallel load is also independent of the state of the clock input or clear input.

Transfer of information to the output pins occurs when the clock input goes from a logical 0 to a logical 1. Since the flip-flops are R-S master-slave circuits, the proper information must appear at the R-S inputs of each flip-flop prior to the rising edge of the clock input voltage waveform. The serial input provides this in- formation to the first flip-flop, while the outputs of the subse- quent flip-flops provide information for the remaining R-S inputs. The clear input must be at a logical 1 and the preset input must be at a logical 0 when clocking occurs.

PL (PARALLEL LOAD)

Ds (SERIAL INPUT)

(CLOCK)

PL Pa Pg Po Pp PE Ds 9396/7496

C di Qp 2B QpQe OO)

PIN NAMES

PL Parallel Load Input Px, Pa, Po, Pp, Pe Parallel Data Inputs Ds Serial Data Input

CP Clock Input

Cc, Clear Input

Qa; Qz, Qe, Qp, QE Parallel Data Outputs

CHARACTERISTICS

CLOCK FREQUENCY 15 MHz PROPAGATION DELAY (CPtoQ) 25ns

POWER DISSIPATION 240 mW PACKAGE 16 Pin DIP (7B)

19

LOADING

5 UL 1 UL 1 UL 1 UL 1 UL 10 UL

STANDARD TTL/MSI ¢ ENCODERS e OPERATORS

9318 8-INPUT PRIORITY ENCODER

DESCRIPTION The 9318 is a multipurpose encoder designed to accept 8 active low inputs and produce a binary weighted output code of the highest order input. A priority is assigned to each active low input so that when two or more inputs are simulta- neously active, the input with the highest priority is represented on the output, with input 7 having the highest priority.

An active low enable input (El) and active low enable output (EO) are provided to expand priority encoding to more inputs. This is accomplished by connecting the more significant encoders enable output (EO) to the next less significant encoder enable input (E1). In addition a group signal is provided which is active if any input is active and El is low.

0123456 7 9318

8 INPUT PRIORITY ENCODER Ao A} GS

LOADING 0 Priority (Active Low) Input 1 UL Tto7 Priority (Active Low) Inputs 2UL EI Enable (Active Low) Input 2 UL EO Enable (Active Low) Output 5 UL Gs Group Select (Active Low) Output 6 UL Ao, Ai, A2 Address (Active Low) Outputs 10 UL

CHARACTERISTICS

TYPICAL DELAY 1TtoA 25ns

PACKAGE 16 Pin Dip (7B) or Flat Pack (4L) TYPICAL POWER DISSIPATION 250 mW

9304 | DUAL FULL ADDER

DESCRIPTION The 9304 consists of two separate high speed binary full adders. The adders are useful in a wide variety of applications including multiple bit parallel add ripple carry addi- tion, parity generation and checking, code conversion, and ma- jority gating. Each adder has the sum and its complement and carry as outputs. Single inversion circuitry is used in the carry logic to provide very low carry through delay (typically 8 ns). The second adder has provisions for either active high or active low inputs at the A and B Operand Inputs.

The adders produce a low carry and both low and high sum with active high inputs, or active high carry and both high and low sum when active low inputs are used. This allows two representa- tions of the logic function which are shown below.

9304 FULL ADDER 1] J FULL ADDER 2 S S$ Co Se 5

PIN NAMES LOADING FULL ADDER 1

A, B Operand Inputs 4UL Cc Carry Input 4UL Ss ‘Sum Output 10 UL s Complementary Sum Output 9 UL Co Carry (Active Low) Output 7 UL FULL ADDER 2

Al OR Operand (Active High) Input 1 UL A2 OR Operand (Active Low) Input 4UL Bi OR Operand (Active High) Input 1UL B2 OR Operand (Active Low) Input 4 UL S Carry (Active Low) Input 4UL S Sum Output 9 UL s Complementary Sum Output 10 UL Co Carry (Active High) Output 7 UL

CHARACTERISTICS

TYPICAL DELAYS AtoS 26 ns A to Co 8ns

PACKAGE 16 Pin Dip (6B) or Flat Pack (4L) TYPICAL POWER DISSIPATION 150 mW

ADDER 1

ADDER 2

STANDARD TTL/MSI © OPERATORS 9324 5-BIT COMPARATOR

DESCRIPTION The 9324 is a high speed expandable comparator which provides comparison between two 5-bit words and gives

three outputs, ‘‘less than,” ‘‘greater than,’’ and ‘‘equal to.’ A

high level on the active low enable input forces all three outputs

low. Ag A] A2A3Aq BoB) B2B3 B4 Words of more than 5 bits may be compared by either connecting 9324 5 BIT COMPARATOR

9324 comparators in series; this is done by connecting the A>B and A<B outputs to the Ao, Bo inputs respectively of the next stage, or by connecting comparators in parallel, and comparing the outputs with another 9324.

TRUTH TABLE PIN NAMES LOADING i = E Enable (Active:Low) Input 2UL E Ae ACB | A>B | A=B Ao, Ai, Ao, Az, As Word A Parallel Inputs 2 UL H X X L L L Bo, Bi, Bz, Bs, Bs Word B Parallel Inputs 2UL L Word A = Word B L L H A<B A Less than B Output 9 UL L Word A > Word B L H L A>B A Greater Than B Output 9 UL L Word B > Word A H L L A=B A Equal to B Output 10 UL

L = Low voltage level = High voltage level ; X = Either high or low voltage level CHARACTERISTICS TYPICAL DELAY DatatoA >B 20ns PACKAGE 16 Pin Dip (7B) or Flat Pack (4L)

TYPICAL POWER DISSIPATION 210 mW

21

STANDARD TTL/MSI OPERATORS 9340

4-BIT ARITHMETIC LOGIC UNIT

DESCRIPTION The 9340 is a high-speed arithmetic logic unit which can perform the arithmetic operations add and subtract on two 4-bit parallel binary words which are represented in 1’s, 2’s complement or sign magnitude notation. The unit can also per- form two logic functions, the actual functions depending upon the polarity of the input operands. These functions, which are controlled by two select inputs, So, Si, are shown for active low input operands below.

9340 4 BIT ARITHMETIC LOGIC UNIT

CO/CG IO

The 9340 incorporates full carry lookahead internally for the 4 bits and provision for external lookahead by using the carry look- ahead functions CP (carry propagate) and CG/CO (carry gen- erate/carry out). The input carry network enables full external

carry lookahead over 16 bits and provides for rippling between PIN NAMES LOADING additional blocks of 12 bits, without additional gates or special Ao, to A3, Bo to B3 Operand (Active Low) Inputs 3 UL carry lookahead IC’s. This ripple block method is operated under So, Si Mode Select Inputs 1 UL control of a COE (carry out enable) input which changes the carry CG. _ First Stage Carry Generate generate into a carry out signal. The delay for various word = (Active Low) Input 3 UL lengths using the built-in carry lookahead circuitry is given below. CP.. First Stage Carry Propagate lf a faster arithmetic unit is required, the 9342 carry lookahead Fre (Active Low) Input TUL aeniis : : rent F G.2 Second Stage Carry Generate eee ed iat with the internal circuitry to provide a {Active Low) Input 2 UL : CP.2 Second Stage Carry Propagate The CP (carry propagate) and CG (carry generate) functions can oa ee ot Woe . 1 UL F . P , 3 Thir tage Carry Generate ee ae ietive Low) np 1UL sree tl aes eae COE | Carry Out Enable Input 1.5 UL ; Fo, Fi, F2, F3 Function (Active Low) Outputs 10 UL CO/CG Carry Out/Carry Generate == (Active Low) Output 10 UL FUNCTION TABLE ACTIVE LOW OPERANDS CP Carry Propagate (Active Low) Output 10 UL So Si FUNCTION DELAY TABLE L Fe ny UET RAGE Se WORD LENGTH ADD SUBTRACT H L A ADD B (in bits) (in ns) (in ns) f : : pe : H = High Voltage Level cd - a L = Low Voltage Level 5-16 42 49 17-28 56 ' 63 29-40 70 7] CHARACTERISTICS 41-52 84 91 TYPICAL DELAYS Addition Over 4 Bits 28ns 53-64 98 105 Addition Over 16 Bits 42 ns 65-76 112 119 PACKAGE 24 Pin Dip (6N) or Flat Pack (4M) 77-88 126 133 TYPICAL POWER 89-100 140 147:

DISSIPATION 400 mw

22

STANDARD TTL/MSI e OPERATORS

9341/54181,74181 4-BIT ARITHMETIC LOGIC UNIT

DESCRIPTION The 9341 is a 4-bit high-speed arithmetic logic unit which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations; the most impor- tant being add and subtract.

Logic and arithmetic operations can be performed for both active j low and active high operands. The function table shows all pos- 9341/54181, 74181

. . . . . . 4 BIT ARITHMETIC sible logic operations for active low and active high operands and LOGIC UNIT

shows arithmetic operations without a carry in for active low and active high operands. When a carry in is supplied, a one is added to all arithmetic terms. For example, A minus B minus 1 without a carry in becomes A minus B (2’s complement subtraction) with a Carry in.

Operation selection is under control of four select lines, So—S3,

and an active low carry enable line. When the internal carries are PIN NAMES LOADING

enabled, the device performs arithmetic. operations; when the Ay to A;; By to B, Operand (Active Low) Inputs 3 UL

carries are inhibited, logic operations results. Thus arithmetic $3.5 ;,S.S; Function Select Inputs AUL

operations are on a word basis while logic operations are on a C. Carry Input 5 UL

Ditpeels: M Mode Control Input 1 UL Cas Carry Output 10 UL

The 9341 incorporates full carry lookahead internal to the 4 bits G Carry Generate (Active Low) Output 10UL

and provision is made for carry lookahead by generation of the P Carry Propagate (Active Low) Output 10 UL

signals P (carry propagate) and G (carry generate). When speed A=B_ Comparator Output 0.C.

requirements are not stringent, the 9341 can be used in a simple Foul tals Function (Active Low) Outputs 10 UL

ripple carry mode by connecting the carry out signal to the O.C. = Open Collector Output,

carry input of the next 4-bit unit. For high-speed operation the CHARACTERISTICS

9341 is used in conjunction with the 9342 carry lookahead cir- TYPICAL DELAYS Addition Over 4 Bits 24 ns

cuit. One carry lookahead package is required for each group Addition Over 16 Bits 36 ns

of four 9341 devices. Carry lookahead can be provided at various PACKAGE 24 Pin Dip (6N) or Flat Pack (4M)

levels thus providing high-speed capability at extremely long TYPICAL POWER

word lengths. DISSIPATION 450 mW

A signal is provided from the 9341 which indicates logic equiva- lence over 4 bits when the unit is in the subtract mode. This signal can be used together with the carry out signal to indicate A >B,A =B.

FUNCTION TABLE

ACTIVE LOW INPUTS ACTIVE HIGH tNPUTS & OUTPUTS & OUTPUTS

33@

MODE SELECT INPUTS

82©

AB minus 1

At+B

A+B

A plus A* AB AB plus A AB AB plus A A

Aplus A* A+B [A+B] plus A A+B [A+B] plusA A

Logical 0 Logical 1

A A minus 1

|

LOGIC ARITHMETIC LOGIC ARITHMETIC 12506 aoe H $3$2S81S9 | (M=H) (M=L)(Cp=H) (M=H) (.M=L)(Cy=L) a Par l LLELL A minus 1 A A JUOOUYDU Lot LH AB minus 1 A+B .) L} \) LLHEL AB minus 1 A+B tL tL HH minus 14 (2's complement) Logical 0 minus 1 (2’s complement) LHLL | AFB Aplus [A+B] AB A plus AB LHLH 1B AB plus [A + B] [A+B] plus